Quantum computers make a lot of tiny mistakes. Error correction is how you still get a reliable answer — by spreading one careful “logical” bit across many physical qubits and checking for slips without destroying the answer.
A new open-access Nature Physics paper from Google Quantum AI shows that the leading method for that job — the surface code — does not have to follow the hardware rules people long treated as fixed. On Willow-class superconducting processors, the team ran three time-dynamic versions of the surface code: one that needs fewer neighbor links per qubit, one where qubits swap “data” and “check” roles each round, and one that uses a different two-qubit gate (iSWAP) instead of the usual CNOT or CZ. All three scaled from distance-3 to distance-5 with state-of-the-art error suppression for each design.
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Why error correction matters in everyday terms
A classical bit is a switch that is either 0 or 1. A qubit can hold a richer state, but that richness is fragile. Noise from the environment, imperfect control pulses, and stray energy levels all nudge qubits off course. If you only run a short experiment, you can sometimes live with the noise. If you want a long computation that stays trustworthy, you need a way to catch and fix mistakes faster than they pile up.
Quantum error correction does that by encoding logical information across many physical qubits and repeatedly measuring “check” patterns (often called syndromes) that reveal errors without reading out the secret answer. The surface code is the workhorse design for many superconducting roadmaps: a grid of data qubits plus measure qubits, with two-qubit gates stitching local parity checks. Until recently, almost every big experiment assumed a square grid, fixed data vs measure roles, and CNOT/CZ-style entangling gates.
The Google team’s point is not that those assumptions were wrong for every chip. It is that dynamic circuits — ones that change shape over time — open other layouts and gates, while still suppressing errors as the code gets larger.
Trick one: a hexagonal layout with fewer connections
Building four good couplings on every qubit is expensive and complicated. The hexagonal surface-code circuit cuts the needed couplings per qubit from four to three. For a distance-5 patch, that meant 49 computational qubits and 64 couplers — about 20% fewer couplers than the 80 used in the standard square layout on the same class of device.
Fewer wires does not mean giving up performance. Using a strong decoder (Harmony with a reinforcement-learning prior), the team measured an error-suppression factor Λ₃₅,hex = 2.15(2) when going from distance-3 to distance-5. That matches the published standard-square result of about Λ₃₅ ≈ 2.14(2). In plain language: making the code larger still cut the logical error rate by a little more than a factor of two per step, even on the sparser wiring graph.
The trick is time-dynamic: each cycle uses a detecting-region pattern that shifts sideways, then a time-reversed cycle that shifts back, so overlapping checks still cover every important place in the circuit. Unused couplers on the chip were biased to zero coupling so the hardware could pretend it was hexagonal.
Trick two: walking — data and measure roles swap
In the textbook surface code, some qubits always hold the logical data and others always run the checks. Data qubits never get a full reset to the ground state during a long memory experiment, so “leakage” — population that sneaks into higher energy levels outside the usual 0/1 computational space — can build up and cause stubborn, time-correlated errors.
A walking circuit flips that script. Each qubit alternates between data and measure roles round by round. Because every qubit is measured (and can be reset) every two cycles, multilevel reset can scrub leakage across the whole patch without a separate data-qubit leakage-removal gadget.
On a 105-qubit Willow-class processor, the distance-5 walking circuit used 58 qubits (a bit more than the usual 49, because walking needs room to move). Logical error rates were ϵ₅ = 0.70(2)% per cycle and a mean ϵ₃ = 1.18(3)% across embedded distance-3 codes, for Λ₃₅,walk = 1.69(6). That is solid suppression, though lower than the hexagonal run — partly because the two-qubit gates on that device were noisier in this configuration. Autocorrelation measurements showed the long leakage “tail” seen in a standard code without dedicated leakage removal was greatly reduced by walking alone.
Trick three: iSWAP instead of CNOT or CZ
Most surface-code experiments entangle qubits with controlled-Z (CZ) or CNOT gates. The iSWAP family — which swaps the |01⟩ and |10⟩ states with a phase — used to look awkward for error correction because it warps the stabilizers so they do not return to a static square pattern. Dynamic circuits fix that by time-reversing every second cycle so the warped “arrowhead” end-cycle shapes still tile into a valid surface-code check pattern.
On the 72-qubit device, the distance-5 iSWAP circuit used 57 qubits. Results: ϵ₅ = 0.650(7)%, mean ϵ₃ = 1.015(6)%, and Λ₃₅,iSWAP = 1.56(2), again without a dedicated data-qubit leakage-removal step beyond multilevel reset. Gate fidelity on this CZ-optimized chip was not ideal for iSWAP — a leftover controlled-phase contributes extra Pauli error — but leakage behavior looked better than a standard CZ run without leakage scrubbing. When the team injected a leaked |2⟩ state, the iSWAP code cleared the spike in a few cycles, closer to a CZ code with leakage removal than to CZ without it.
What “distance” and Λ really mean here
Code distance is a size label: a larger distance can tolerate more simultaneous mistakes before the logical bit flips. Comparing distance-3 to distance-5 is the field’s standard “does bigger help?” test. The ratio Λ₃₅ = ϵ₃ / ϵ₅ is the suppression factor — how much the logical error rate drops when you take that step. Values above 1 mean scaling helps; the hexagonal result matching the prior square-lattice record is the headline that hardware designers will notice.
These were logical memory experiments: prepare a logical X or Z state, run many error-correction cycles, then measure. That is not a full algorithm, but it is the right first proof that a circuit family can suppress errors as you grow the code.
Why this matters beyond one paper
Chip designers have spent years optimizing square grids for CZ gates. This work says you can co-design the error-correction circuit with the wiring graph and the native gate set. Fewer couplers can simplify fabrication and frequency planning. Walking builds leakage cleanup into the schedule. iSWAP may suit devices whose best entangling interaction is not CZ. Simulations in the paper even suggest that hardware tailored to a hexagonal layout could improve Λ by roughly 15% while cutting connection count.
None of this erases the hard parts — better gates, better readout, and still-larger distances remain necessary for useful fault-tolerant machines. It does widen the menu. Dynamic surface codes show that “how you check for mistakes” can flex with the hardware you actually know how to build.
Further reading
Quantum Computing for Everyone — Chris Bernhardt’s clear MIT Press intro to qubits, gates, and algorithms — written for readers comfortable with high-school math.
Something Deeply Hidden — Sean Carroll’s tour of quantum foundations and many-worlds — useful background for why quantum systems are so hard to keep error-free.